Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, Forming an electrical interconnection with a transistor source/drain region, and integrated circuitry

ABSTRACT

In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate. Conductive material is formed which is received within at least one of the isolation regions. In one preferred implementation, a silicon-on-insulator (SOI) substrate is utilized to support integrated circuitry which is formed utilizing the methodical aspects of the invention. In another preferred implementation, other substrates, such as conventional bulk substrates are utilized.

TECHNICAL FIELD

[0001] This invention relates to semiconductor processing methods offorming integrated circuitry, forming conductive lines, forming aconductive grid, forming a conductive network, forming an electricalinterconnection to a node location, forming an electricalinterconnection with a transistor source/drain region, and relatedintegrated circuitry.

BACKGROUND OF THE INVENTION

[0002] Semiconductor device fabrication typically involves fabricationof transistors relative to a substrate. One type of transistor is a MOStransistor which includes a conductive gate and diffusion regions whichserve as the source and drain of the transistor. Individual transistorsare often separated from one another by isolation regions which serve toelectrically insulate transistor components from one another. One typeof substrate upon which such transistors can be formed is asilicon-on-insulator (SOI) substrate which comprises individual islandsof semiconductive material formed atop and surrounded by insulatormaterial, which is typically an oxide material. Transistors are formedover or within semiconductive islands, with insulator materialseparating the islands. Another type of substrate upon which suchtransistors can be formed is a bulk semiconductive substrate such asmonocrystalline silicon. Such substrates typically comprise active areaswithin which desired transistors are formed, with such areas beingseparated by oxide isolation regions.

[0003] Typically, electrical interconnections between transistors orother devices are formed by providing an insulating layer of materialover the substrate and an associated transistor location with whichelectrical connection is desired, and then etching a contact openingthrough the insulating material to the transistor location.Subsequently, conductive material is deposited to within the contactopening and electrically connects with the desired transistor location.Forming an interconnection in this manner requires at least oneadditional layer of material (the BPSG material) and additionalprocessing steps which prolong the fabrication process.

[0004] One type of integrated circuitry in which the above electricalinterconnections can be made is dynamic random access memory (DRAM)circuitry. DRAM cells utilize storage capacitors which are operablyassociated with MOS transistors. Storage capacitors are typically formedwithin and relative to insulating material which is formed over thesubstrate. The amount of charge a particular capacitor can store isproportional to the amount of capacitor storage node surface area. AsDRAM dimensions grow smaller, there is a push to maintain storagecapacitance values despite denser circuitry.

[0005] This invention grew out of concerns associated with improving themanner in which wafer space is utilized to support integrated circuitryconstructions. This invention also grew out of concerns associated withimproving the manner in which integrated circuitry electricalinterconnections are formed.

SUMMARY OF THE INVENTION

[0006] In one aspect, the invention provides a method of forming anelectrical connection in an integrated circuitry device. According toone preferred implementation, a diffusion region is formed insemiconductive material. A conductive line is formed which is laterallyspaced from the diffusion region. The conductive line is formed relativeto and within isolation oxide which separates substrate active areas.The conductive line is subsequently interconnected with the diffusionregion. According to another preferred implementation, an oxideisolation grid is formed within semiconductive material. Conductivematerial is formed within the oxide isolation grid to form a conductivegrid therein. Selected portions of the conductive grid are then removedto define interconnect lines within the oxide isolation grid. Accordingto another preferred implementation, a plurality of oxide isolationregions are formed over a semiconductive substrate. Conductive materialis formed which is received within at least one of the isolationregions.

[0007] In one preferred implementation, a silicon-on-insulator (SOI)substrate is utilized to support integrated circuitry which is formedutilizing the methodical aspects of the invention. In another preferredimplementation, other substrates, such as conventional bulk substratesare utilized.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0009]FIG. 1 is a diagrammatic section view of a portion of asemiconductor wafer at one processing step of a processing method inaccordance with the invention.

[0010]FIG. 2 is a diagrammatic section of the FIG. 1 semiconductor waferportion at a processing step which is subsequent to that shown in FIG.1.

[0011]FIG. 3 is a diagrammatic section of the FIG. 1 semiconductor waferportion at a processing step which is subsequent to that shown in FIG.2.

[0012]FIG. 4 is a diagrammatic section of the FIG. 1 semiconductor waferportion at a processing step which is subsequent to that shown in FIG.3.

[0013]FIG. 5 is a diagrammatic section of the FIG. 1 semiconductor waferportion at a processing step which is subsequent to that shown in FIG.4.

[0014]FIG. 6 is a diagrammatic section of the FIG. 1 semiconductor waferportion at a processing step which is subsequent to that shown in FIG.5.

[0015]FIG. 7 is a diagrammatic section of the FIG. 1 semiconductor waferportion at a processing step which is subsequent to that shown in FIG.6.

[0016]FIG. 8 is a diagrammatic section of the FIG. 1 semiconductor waferportion at a processing step which is subsequent to that shown in FIG.7.

[0017]FIG. 9 is a diagrammatic section of the FIG. 1 semiconductor waferportion at a processing step which is subsequent to that shown in FIG.8.

[0018]FIG. 10 is a diagrammatic section of the FIG. 1 semiconductorwafer portion at a processing step which is subsequent to that shown inFIG. 9.

[0019]FIG. 11 is a diagrammatic section of the FIG. 1 semiconductorwafer portion at a processing step which is subsequent to that shown inFIG. 10.

[0020]FIG. 12 is a diagrammatic section of the FIG. 1 semiconductorwafer portion at a processing step which is subsequent to that shown inFIG. 11.

[0021] FIG, 13 is a diagrammatic section of the FIG. 1 semiconductorwafer portion at a processing step which is subsequent to that shown inFIG. 12.

[0022]FIG. 14 is a diagrammatic section of the FIG. 1 semiconductorwafer portion at a processing step which is subsequent to that shown inFIG. 13.

[0023]FIG. 15 is a diagrammatic section of the FIG. 1 semiconductorwafer portion at a processing step which is subsequent to that shown inFIG. 14.

[0024]FIG. 16 is a diagrammatic section of the FIG. 1 semiconductorwafer portion at a processing step which is subsequent to that shown inFIG. 15.

[0025]FIG. 17 is a diagrammatic section of the FIG. 1 semiconductorwafer portion at a processing step which is subsequent to that shown inFIG. 16.

[0026]FIG. 18 is a diagrammatic section of the FIG. 1 semiconductorwafer portion at a processing step which is subsequent to that shown inFIG. 17.

[0027]FIG. 19 is a diagrammatic section of the FIG. 1 semiconductorwafer portion at a processing step which is subsequent to that shown inFIG. 18.

[0028]FIG. 20 is a diagrammatic section of the FIG. 1 semiconductorwafer portion at a processing step which is subsequent to that shown inFIG. 19.

[0029]FIG. 21 is a top plan view of the FIG. 1 semiconductor waferportion at a processing step just after the processing step shown inFIG. 1.

[0030]FIG. 22 is a top plan view of the FIG. 1 semiconductor waferportion at a processing step just after the processing step shown inFIG. 5.

[0031]FIG. 23 is a top plan view of the FIG. 1 semiconductor waferportion at a processing step intermediate the processing steps shown inFIGS. 7 and 8.

[0032]FIG. 24 is a diagrammatic section view of a semiconductor wafer atone processing step of a processing method in accordance with analternate embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0034] Referring to FIG. 1, a fragmentary portion of a semiconductorwafer is designated by reference numeral 10. Wafer 10 constitutes aportion of integrated circuitry which is fabricated relative to asemiconductive substrate 12 which constitutes a portion of asemiconductive material-on-insulator (SOI) substrate. In the context ofthis document, the term “semiconductive substrate” is defined to meanany construction comprising semiconductive material, including, but notlimited to, bulk semiconductive materials such as a semiconductive wafer(either alone or in assemblies comprising other materials thereon), andsemiconductive material layers (either alone or in assemblies comprisingother materials). The term “substrate” refers to any supportingstructure, including, but not limited to, the semiconductive substratesdescribed above. Substrate 12 preferably comprises a portion of a bulkmonocrystalline silicon substrate and supports a layer of insulativematerial 14 thereover. An exemplary material is SiO₂. A plurality ofupstanding silicon-containing structures or semiconductive materialislands 16 are formed over insulative material 14. Individual structuresor islands 16 include respective sidewalls 18. Adjacent sidewalls 18 ofdifferent structures or islands 16 face one another and definerespective separation distances d or spaces relative to and betweenother adjacent silicon-containing structures or islands.

[0035] Structures or islands 16 constitute spaced apart semiconductivematerial islands which are surrounded and separated by insulatingmaterial 20. Material 20 is formed in the spaces between the individualadjacent islands or structures. Individual structures 16 includerespective outer surfaces 22, Nitride-containing caps 24 are formed overouter surfaces 22. Example individual silicon-containing islandthickness is from about 1000-5000 Angstroms. Example thicknesses forindividual nitride-containing caps 24 are from about 2000-4000Angstroms. An exemplary material for caps 24 is Si₃N₄. Additionally,insulating material 20 is formed over the substrate and then preferablyplanarized as by suitable mechanical abrasion of the substrate to adegree which is sufficient to leave it generally coplanar with thenitride-containing caps 24. Such defines an outer plane 26. Accordingly,the entirety of the corresponding separation spaces between respectiveislands or structures 16 are occupied with the insulating material. Anexemplary material for insulating material 20 is Si0 ₂ deposited bychemical vapor deposition.

[0036] One exemplary manner of forming the preferred silicon-containingstructures 16 is as follows. A blanket pad structure is formed on asilicon-containing wafer. Preferably the blanket structure comprises athin thermal oxide film and a thick nitride layer (Si₃N₄) which coversthe thin oxide film. A first island pattern and etch is conducted whichetches into the silicon-containing wafer to a desired depth. Such firstetch defines a plurality or series of strips or bars which partiallydefine island length or width dimensions. Such etch also defines anelevational depth of the islands to be formed. Insulating material;preferably SiO₂, can then be chemical vapor deposited into the strips orbars and planarized as by suitable mechanical abrasion of the substrate,with such planarization terminating at the nitride layer.

[0037] Subsequently, a second island pattern and etch can be conductedwhich etches into the silicon-containing wafer to a desired depth. Suchsecond etch preferably defines a plurality or series of strips or barswhich are generally orthogonally disposed relative to the strips or barsdefined by the first island pattern and etch. The collective first andsecond etches define individual island length, width and, to a certainextent, depth dimensions.

[0038] Nitride spacers are then formed over the island portions whichwere exposed by the second etch, island portions which were exposed bythe first etch being covered by the SiO₂ insulating material mentionedabove. Subsequently, an isotropic etch of silicon-containing material isconducted to a degree which is sufficient to completely undercut thematerial and to form the preferred islands constructions. Such undercutislands are supported relative to the substrate by the previously formedSiO₂ insulating material which was deposited after the first islandpattern and etch. Following the undercut etch, insulative material suchas thermally grown oxide is formed beneath the islands to support thesame relative to the substrate. Such insulative material corresponds toinsulative material 14 of FIG. 1. An etch to remove the nitride spacerscan be conducted at this point and subsequent insulating material can bechemical vapor deposited in the regions laterally adjacent theindividual islands. Such insulating material corresponds to a portion ofmaterial 20 in FIG. 1. Subsequent planarization of the insulatingmaterial provides a wafer construction such as that shown in FIG. 1.

[0039] Alternately, the FIG. 1 construction could be provided bydepositing an oxide layer over a bulk substrate, followed by depositinga silicon layer and a nitride layer. Patterning could then be conducted.Oxide would thereafter be deposited and planarized back to produce theFIG. 1 construction.

[0040] Collectively, insulating material 20 and underlying insulativematerial 14 constitute an isolation oxide grid which effectivelyseparates the individual islands and electrically insulates the samefrom one another. FIG. 21 is a top view of wafer 10 and shows a portionof the isolation oxide grid at 21. Some of the insulating material 20(FIG. 1) constitutes isolation oxide regions which are formed laterallyadjacent the semiconductive material which constitutes individualislands 16. Such isolation oxide regions also include insulatingmaterial 20 which is formed laterally adjacent respective nitridecontaining caps 24.

[0041] Referring to FIG. 2, at least some of insulating material 20occupying corresponding separation distances d is removed, such as byetching, to a degree effective to expose at least a portion ofrespective sidewalls 18 of adjacent islands 16. As shown, a portion ofinsulative layer 14 is also etched. Such etch constitutes an etch of theabove-mentioned isolation oxide regions to a point which will beelevationally below conductive diffusion regions which are to be formedrelative to islands 16, as will become apparent below. Moreover, suchetch can be considered as part of the formation of a conductive linewhich is to be ultimately in electrical communication with one of thediffusion regions to be formed. The depth of such etch can extendelevationally downward to and terminate at the underlying siliconsubstrate 12. Preferably, the etch does not extend into substrate 12. Inthe illustrated example, such etch stops short of substrate 12 andetches into a portion of insulative material 14.

[0042] The illustrated etch defines a plurality or network of respectiveoutwardly-exposed elongated trenches 28 between respective sidewalls 18of laterally adjacent islands 16. As so formed, the trenches haverespective lateral widths W in lateral width directions which lie in theplane of the page upon which FIG. 2 appears. In the illustrated example,each trench width W is approximately equal to the separation distance dbetween adjacent islands, owing to the fact that most, if not all of thecorresponding isolation oxide formerly occupying that area has beenremoved. The trench width can be less than the separation distance.

[0043] Alternately considered, islands 16 constitute a plurality ofupstanding silicon-containing structures which are formed overinsulative oxide layer material 14. A network of conduits are formed ordefined within the insulative material and between the individualislands. One implementation of the conduits constitutes theabove-described trenches 28. Other conduit constructions are possible.As will become apparent below, the conduits provide a mechanism by whicha conductive grid can be formed.

[0044] Referring to FIG. 3, additional insulating material 30 is formedover the exposed island sidewalls 18 and to a degree which is sufficientto leave at least a portion of individual separation distances dunoccupied with any of the additional insulating material. Theillustrated separation distances which are unoccupied with any of theadditional insulating material are designated at d₁. In the illustratedand preferred embodiment, insulating material 30 constitutes a lining ofSiO₂ which is chemical vapor deposited to a thickness which isapproximately one third (⅓) of the separation distance d. Accordingly,d₁ is approximately equal to one third (⅓) of the separation distance d.Other spatial relationships are of course possible. As so formed ordeposited, the oxide lining material 30 fills about two thirds (⅔) ofthe lateral width of each respective trench 28 in the lateral widthdirection to form associated troughs 29 for receiving conductivematerial described just below.

[0045] Referring to FIG. 4, a first conductive material 32 is formedover the substrate, within each etched oxide isolation region and overoxide lining material 30 within each trough 29. In the illustrated andpreferred embodiment, the conductive material is chemical vapordeposited and constitutes a suitable conductive material. Exemplarymaterials include polysilicon, either conductive as deposited andrendered conductive thereafter, and suitable refractory metals.Accordingly, first conductive material 32 is formed in the remainingportion of trench 28 which is unoccupied with any of the oxide liningmaterial 30 (i.e. troughs 29). Accordingly, conductive material 32replaces at least some of the etched insulating material 20 (FIG. 2)which was previously removed between islands 16. Some conductivematerial which replaces the etched insulating material is disposedlaterally adjacent and between respective islands 16. As so formed, theconductive material is laterally spaced from conductive diffusionregions which are to be formed relative to islands 16 and which aredescribed in detail below.

[0046] Referring to FIG. 5, conductive material 32 is planarized as bysuitable mechanical abrasion of substrate 12 to a degree which issufficient to isolate desired conductive material 32 relative to otherlaterally spaced conductive material. Such also preferably removes oxidelining material 30 which directly overlies (FIG. 4) the respectivenitride-containing caps 24 which serve as a stopping level for theplanarization step. Accordingly, the planarization defines a conductivenetwork or grid which is formed within the isolation oxide. FIG. 22 is atop view of wafer 10 and shows a portion of the conductive network orgrid at 23. The planarized oxide lining material 30 (FIG. 5) andconductive material 32 are substantially coplanar with thenitride-containing caps 24 at plane 26.

[0047] Referring to FIG. 6, the resulting conductive material 32 isselectively etched or otherwise recessed to below an immediatelyadjacent planar surface, here, the outer surface of thenitride-containing caps 24. Preferably, material 32 is recessed about1000 Angstroms inwardly relative to the immediately adjacent planarsurface. As so recessed, the remaining conductive material constitutes arecessed conductive grid which is formed relative to and running withinthe oxide isolation grid.

[0048] Referring to FIG. 7, selected substrate areas are masked withphotoresist 34. Such defines respective exposed areas, such as area 36,within which selected conductive material 32 is to be removed.

[0049] Referring to FIG. 8, conductive material is removed, such as byetching, from the unmasked substrate areas leaving the correspondingtroughs 29 in area 36 empty. The removal of selected portions of theconductive material grid constitutes a definition step in which aplurality of interconnect lines are formed within the oxide isolationgrid which corresponds to those areas which were masked. In theillustrated embodiment, the selected conductive material can be andpreferably is removed by an etch which is selective to SiO₂ (the oxidelining material) and the nitride material from which caps 24 are formed(i.e. Si₃N₄).

[0050]FIG. 23 is a top plan view of a portion of substrate 10immediately following the removal of the selected portions of theconductive material grid and the stripping of photoresist justdiscussed. Accordingly, a plurality of exposed nitride-containing caps24 which overlie associated silicon-containing islands 16 (FIG. 8) areshown. Selected areas or spaces between the caps contain dashed linesand represent the trenches from which conductive material has beenremoved. Exemplary areas are designated by reference numeral 25. Otherareas, designated at 27, represent the trenches from which conductivematerial was not removed. Accordingly, such trenches 27 constitute someof the interconnect lines at least some of which will eventually beelectrically interconnected to diffusion regions to be formed.

[0051] Referring back to FIG. 8 and following removal of the FIG. 7photoresist 34, a layer of insulative material 38 is formed oversubstrate 12 as shown. Insulative material 38 preferably constitutes anoxide material such as SiO₂ which is chemical vapor deposited to adegree sufficient to fill in the empty troughs 29 from which conductivematerial was previously removed and to cover conductive material 32which was not removed.

[0052] Referring to FIG. 9, insulative material 38 is planarized as bysuitable mechanical abrasion to be substantially coplanar withnitride-containing caps 24.

[0053] Referring to FIG. 10, the nitride-containing caps are strippedaway to outwardly expose the respective outer surfaces 22 of thesilicon-containing structures or islands 16. The respective outersurfaces 22 define portions of individual active areas in whichdiffusion regions are to be formed. At this point, and in advance offorming the diffusion regions, however, threshold voltage implantationscan take place to adjust the respective threshold voltages of transistorgates which are to be formed over and atop structures 16.

[0054] Referring to FIG. 11, individual gate oxide layers 40 are formedover the respective silicon-containing structure outer surfaces.Subsequently, a polysilicon layer 42 is formed over respective gateoxide layers 40. Other materials suitable for use in forming transistorgates can be utilized.

[0055] The polysilicon material of layer 42 is then planarized as bysuitable mechanical abrasion. The planarized polysilicon material isthen recessed using a selective etch. An exemplary depth of such recessis about 500 Angstroms. Subsequently, an oxide layer is formed over therecessed polysilicon. Such can be accomplished through thermal oxidationor through chemical vapor deposition of SiO₂. An exemplary thickness ofsuch formed oxide layer is about 1000 Angstroms. After the oxide layerformation, subsequent planarization thereof results in the FIG. 12structure, where respective resultant oxide caps are shown at 44. Suchprovides a plurality of stack structures which are formed overindividual silicon-containing structures 16 and between isolation oxidewhich extends outward of the individual islands or structures. Each suchstack structure constitutes multiple transistor-forming layers whichinclude layers 40, 42, and 44.

[0056] Referring to FIG. 13, individual stack structures are patternedand etched to form individual gate structures or transistor gates 46over the silicon-containing structures 16.

[0057] Referring to FIG. 14, insulative or insulating sidewall spacers48 are formed over respective sidewalls of the individual transistorgates 46. Conductive source/drain diffusion regions or node locations 50are formed within the semiconductive material which constitutesindividual islands 16. Each diffusion region 50 has an associated outersurface 52. In the illustrated and preferred embodiment, remainingconductive material 32 constitutes a conductive line a portion of whichis laterally spaced from structure 16 and associated diffusion regions50. A predominate portion and preferably all of the conductive line isdisposed elevationally below the diffusion region outer surface 52 asshown. In the illustrated example, each diffusion region is formedbetween spaced apart isolation oxide regions. Portions of such spacedapart isolation oxide regions are shown to extend elevationally above oroutward of and adjacent the respective islands in which such diffusionregions are formed. Other portions of some of the same isolation oxideregions are shown to contain conductive material 32.

[0058] Referring to FIG. 15, insulative material 54 is formed over thesubstrate and to a degree which is sufficient to cover the individualtransistor gates 46 and each's associated diffusion regions 50.Exemplary insulative materials include SiO₂ and other suitableinsulators.

[0059] Referring to FIG. 16, insulative material 54 is planarized as bysuitable mechanical abrasion.

[0060] Referring to FIG. 17, a layer of masking material 56 is formedover insulative material 54 and patterned to define a mask opening 58elevationally over the conductive material of line 32. Preferably themask opening overlaps with a portion of one of the diffusion regions 50so that a subsequent etch can outwardly expose at least a portion ofboth the diffusion region and the conductive line.

[0061] Referring to FIG. 18, insulative material 54 is so etched tooutwardly expose a portion of the illustrated diffusion region 50 andconductive material 32. Masking material 56 (FIG. 17) is subsequentlyremoved.

[0062] Referring to FIG. 19, a second conductive material 60 is formedover the substrate, the exposed diffusion region 50 and the conductivematerial 32 and forms a connective electrical interconnection betweenthe latter components. The first conductive material 32 and the secondconductive material 60 can comprise the same or different materials.Exemplary materials include doped polysilicon or undoped polysiliconwhich is subsequently rendered conductive by masked doping implants.Other suitable materials include refractory metals. A preferred mannerof forming material 60 over the substrate is by chemical vapordeposition.

[0063] Referring to FIG. 20, material 60 is planarized as by suitablemechanical abrasion to form the preferred conductive network.

[0064] The above-described methodology is directed to fabrication of thepreferred integrated circuitry utilizing an SOI substrate. For purposesof illustration only, the above has been described in the context offorming only one transistor relative to an associated silicon-containingisland. More than one transistor, however, can be formed atop anindividual island. For example, in the context of dynamic random accessmemory (DRAM) devices, suitably dimensioned islands can be formed forsupporting and accommodating multiple transistor constructions whichconstitute the DRAM's memory cells (e.g. - access transistors andstorage capacitors).

[0065] Referring to FIG. 24, an alternate construction and one which isappropriate for use in connection with conventional bulk silicontechnology is set forth. Accordingly, a semiconductor wafer fragment isindicated generally by reference numeral 10 a. Such comprises a bulksilicon substrate 62. A plurality of laterally spaced isolation trenches64, 66 are conventionally formed within the substrate and thereafterfilled with isolation oxide 68 to define isolation oxide regions. Theisolation oxide regions define therebetween a substrate active area. Inthe illustrated example, a single transistor construction 69 issupported by the substrate active area. More than one transistorconstruction can be supported by such active areas. As so formed, theisolation trenches are disposed laterally adjacent the substrate activearea. Each isolation oxide region has a lateral width which lies in theplane of the page upon which FIG. 24 appears. In accordance with theinventive methodical aspects described above, some of the isolationoxide, preferably portions which are disposed intermediate the lateralwidth are removed. Such corresponds to the left-most isolation oxideregion. In both the SOI and the bulk embodiments, the removed isolationoxide is preferably greater in an elevationally downward direction thana laterally outward direction. Some of the removed isolation oxide isthereafter replaced with first conductive material 70. Conductivematerial 70 as so formed is disposed laterally adjacent one of a pair ofsource/drain diffusion regions 72 which forms part of the transistorconstruction 69. The diffusion region 72 closest to conductive material70 constitutes a node location with which electrical connection is to bemade. An insulative material 73 is formed over the substrate andsubsequently etched to outwardly expose at least some of both of theconductive material 70 and the diffusion region 72. Second conductivematerial 74 is formed over the first conductive material the adjacentdiffusion region 72 to provide an electrical connection therebetween.The first and second conductive materials can constitute the same ordifferent materials, such materials being discussed above in connectionwith the SOI embodiment. As so formed, the predominate portion of firstconductive material 70 extends below the diffusion region outer surface.

[0066] Although the bulk embodiment has been described in the context ofisolation oxide regions which are formed utilizing a trench and refilltechnique, other methods of forming the oxide isolation regions, such aslocal oxidation of silicon (LOCOS) can be used. And, as with the SOIembodiment, the conventional bulk embodiment can be modified to supportmore than one transistor construction which, by way of example, would besuitable for use in forming DRAM memory cells. Accordingly, suchintegrated memory circuitry, whether fabricated in connection with theSOI or bulk embodiments constitutes a plurality of source/draindiffusion regions which are supported by an appropriate substrate. Aplurality of isolation oxide regions are supported by the substrate andinterposed between and separate at least some of the diffusion regions.A plurality of conductive lines are supported by the substrate asdescribed above, at least some of which being operatively connected withat least some of the diffusion regions and disposed within an associatedisolation oxide region.

[0067] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of forming an electrical connection with a transistorsource/drain region of an SOI transistor comprising: forming a pluralityof spaced apart semiconductive material islands over an insulativematerial, individual islands comprising respective outer surfaces;forming a conductive transistor gate over at least some of the outersurfaces; forming at least one conductive source/drain diffusion regionwithin semiconductive material laterally adjacent at least one of thegates; forming a first conductive material between at least some of theislands and laterally spaced from the one source/drain diffusion region,the first conductive material extending elevationally below the outersurface over which the one conductive gate is formed; and forming asecond conductive material over and in electrical connection with thefirst conductive material and the one source/drain diffusion region toprovide an electrical connection.
 2. The method of forming an electricalconnection with a transistor source/drain region of claim 1, wherein theforming a first conductive material comprises: etching insulatingmaterial between adjacent islands; and replacing at least some of theetched insulating material with the first conductive material.
 3. Themethod of forming an electrical connection with a transistorsource/drain region of claim 1, wherein: the islands define respectiveseparation spaces between adjacent islands, at least some of theseparation spaces being occupied with insulating material; and theforming of the first conductive material comprises: removing at leastsome of the insulating material occupying at least one of the separationspaces; and replacing at least some of the removed insulating materialwith first conductive material to a degree sufficient to only partiallyoccupy the one separation space with first conductive material.
 4. Themethod of forming an electrical connection with a transistorsource/drain region of claim 1, wherein: individual islands haverespective sidewalls and define respective separation spaces betweenadjacent island sidewalls, at least some of the separation spacesbetween island sidewalls being occupied with insulating material; andthe forming of the first conductive material comprises: a etching atleast some of the insulating material occupying at least one of theseparation spaces to a degree sufficient to expose at least a portion ofan island sidewall; forming additional insulating material over theexposed island sidewall portion and to a degree sufficient to leave atleast a portion of the separation space unoccupied with any additionalinsulating material; and forming first conductive material within theremaining unoccupied separation space.
 5. A method of forming anelectrical connection comprising: forming a diffusion region insemiconductive material, the diffusion region having an outer surface;forming a conductive line laterally spaced from the semiconductivematerial and diffusion region, a predominate portion of the conductiveline being disposed elevationally below the diffusion region outersurface; and interconnecting the conductive line and the diffusionregion with electrically conductive material.
 6. The method of claim 5,wherein interconnecting the conductive line and the diffusion regioncomprises forming the electrically conductive material,, over both theconductive line and the diffusion region.
 7. The method of claim 5,wherein the forming of the conductive line comprises: forming anisolation oxide region laterally adjacent the semiconductive material,the oxide region having a lateral width; removing a portion of theisolation oxide intermediate the lateral width; and replacing at leastsome of the removed isolation oxide with electrically conductivematerial.
 8. The method of claim 5, wherein the forming of theconductive line comprises: forming an isolation oxide region laterallyadjacent the semiconductive material, the oxide region having a lateralwidth; removing a portion of the isolation oxide intermediate thelateral width and to a greater degree in an elevationally downwarddirection than a laterally outward direction; and replacing at leastsome of the removed isolation oxide with electrically conductivematerial.
 9. The method of claim 5, wherein the forming of theconductive line comprises: forming an isolation oxide region laterallyadjacent the semiconductive material, the oxide region having a firstlateral width; removing a portion of the isolation oxide at leastintermediate the lateral width; forming oxide material within the firstlateral width and to a degree sufficient to occupy less than the firstlateral width and to define a second lateral width; and replacing atleast some of the removed isolation oxide with electrically conductivematerial.
 10. A method of forming at least one interconnection to a nodelocation in SOI integrated circuitry comprising: forming a conductivediffused node location in a silicon-containing structure, the structurebeing formed over and surrounded by isolation oxide; forming a firstconductive material laterally adjacent the silicon-containing structure,a predominate portion of the first conductive material being disposedelevationally below the diffused node location; and forming a secondconductive material over at least a portion of the first conductivematerial and the node location to provide an electrical interconnectiontherebetween.
 11. The method of claim 10, wherein the first conductivematerial and the second conductive material comprise the same material.12. The method of claim 10, wherein the first conductive material andthe second conductive material comprise the different materials.
 13. Themethod of claim 10, wherein the forming a first conductive materialcomprises: etching the isolation oxide and exposing at least a portionof the silicon-containing structure, the etching defining an elongatedtrench for receiving first conductive material; and filling at least aportion of the trench with first conductive material.
 14. The method ofclaim 10, wherein the forming a first conductive material comprises:etching the isolation oxide and exposing at least a portion of thesilicon-containing structure, the etching defining an elongated trenchfor receiving first conductive material; depositing an oxide materialwithin the trench and over the exposed portion of the silicon-containingstructure, the oxide material defining a trough within the trench; andfilling at least a portion of the trough with first conductive material.15. The method of claim 10, wherein the forming a first conductivematerial comprises: etching the isolation oxide to a degree sufficientto expose a silicon-containing sidewall of the silicon-containingstructure and a silicon-containing sidewall of another laterallyadjacent silicon-containing structure, the two silicon-containingsidewalls generally facing one another and defining a trenchtherebetween; forming an oxide lining within the trench and over the twosilicon-containing sidewalls, the oxide lining defining a trough withinthe trench; and forming first conductive material within at least aportion of the trough and over at least some of the oxide lining.
 16. Amethod of forming integrated circuitry comprising: forming a diffusionregion within semiconductive material between spaced apart isolationoxide regions; forming a conductive line within at least one of theisolation oxide regions adjacent the diffusion region; and formingconductive material over the diffusion region and the conductive line toprovide an electrical interconnection therebetween.
 17. The method offorming integrated circuitry of claim 16, wherein the forming aconductive line comprises: etching the one isolation oxide region toelevationally below the diffusion region; and forming conductive linematerial within the one isolation region.
 18. The method of formingintegrated circuitry of claim 16, wherein the forming a conductive linecomprises: etching the one isolation oxide region to elevationally belowthe diffusion region, the etching defining a lateral width dimension ina width dimension direction; forming oxide material within the lateralwidth dimension and to a degree sufficient to: occupy about two thirdsof at least some of the lateral width dimension in the width dimensiondirection; and forming conductive line material in at least some of thelateral width dimension which is not occupied with oxide material.
 19. Amethod of forming an electrical connection to a node locationcomprising: forming at least one isolation trench within a bulksemiconductive substrate, the isolation trench being disposed laterallyadjacent a substrate active area; filling the one isolation trench withisolation oxide; removing some of the isolation oxide from the oneisolation trench; replacing the removed isolation oxide with firstconductive material; forming a diffusion region in the substrate activearea, the diffusion region defining a node location to which electricalconnection is to be made; and forming second conductive material overthe first conductive material and the diffusion region to provide anelectrical connection therebetween.
 20. The method of forming anelectrical connection to a node location of claim 19, wherein thediffusion region has an outer surface and the first conductive materialis formed to extend predominately below the diffusion region outersurface.
 21. The method of forming an electrical connection to a nodelocation of claim 19 further comprising forming at least one conductivegate within the active area.
 22. The method of forming an electricalconnection to a node location of claim 19, wherein: the forming of theone isolation trench comprises forming at least two isolation trencheswhich are laterally spaced from one another, the trenches beingthereafter filled with isolation oxide; and the removing comprisesremoving only some isolation oxide from both trenches, the removedisolation oxide being thereafter replaced with first conductivematerial.
 23. The method of forming an electrical connection to a nodelocation of claim 19, wherein the first conductive material and thesecond conductive material comprise the same material.
 24. The method offorming an electrical connection to a node location of claim 19, whereinthe first conductive material and the second conductive materialcomprise different materials.
 25. A method of forming conductive linescomprising: forming an oxide isolation grid between semiconductivematerial; forming conductive material within the oxide isolation grid toform a conductive grid therein; and removing selected portions of theconductive material grid to define interconnect lines within the oxideisolation grid.
 26. The method of forming conductive lines of claim 25,wherein the forming an oxide isolation grid comprises forming individualoxide isolation regions over a semiconductive substrate by trench andrefill technique.
 27. The method of forming conductive lines of claim25, wherein the forming an oxide isolation grid comprises: forming aplurality of silicon-containing islands over an insulative surface; andforming oxide isolation regions between silicon-containing islands. 28.The method of forming conductive lines of claim 25, wherein the formingconductive material within the oxide isolation grid comprises: etchinginto the oxide isolation grid to define a network of outwardly-exposedtrenches running within the oxide isolation grid; forming conductivematerial within and over the outwardly-exposed trenches to a degreesufficient to completely fill the trenches; and planarizing theconductive material to isolate conductive material within the trenchesand to define the conductive grid.
 29. A method of forming a conductivegrid over a substrate comprising: forming a layer of insulative materialover a substrate surface; forming a plurality of upstandingsilicon-containing structures over the insulative material, thesilicon-containing structures comprising respective outer surfaces;defining a network of conduits within the insulative material betweenindividual silicon-containing structures; and filling the conduits atleast partially with conductive material to provide a conductive grid.30. The method of forming a conductive grid of claim 29, whereindefining a network of conduits comprises etching at least some of theinsulative material between individual silicon-containing structures tobelow an adjacent silicon-containing outer surface.
 31. The method offorming a conductive grid of claim 29, wherein: the defining a networkof conduits comprises etching at least some of the insulative materialbetween individual silicon-containing structures to a degree sufficientto expose respective silicon-containing structure sidewalls; and priorto filling the conduits at least partially with conductive material,forming an oxide lining material within the conduits and over theexposed respective silicon-containing structure sidewalls.
 32. A methodof forming a conductive network comprising: forming a plurality of oxideisolation regions over a semiconductive substrate; and formingconductive material received within at least one of the oxide isolationregions.
 33. The method of forming a conductive network of claim 32,wherein the forming a conductive material comprises: etching into atleast some oxide isolation region material; forming conductive materialwithin the etched oxide isolation regions; and planarizing theconductive material to a degree sufficient to isolate desired conductivematerial relative to other conductive material, the planarizing definingthe conductive network.
 34. The method of forming a conductive networkof claim 32, wherein the forming a conductive material comprises:etching into at least some oxide isolation region material; chemicalvapor depositing an oxide lining material within the etched isolationregions; forming conductive material within the etched oxide isolationregions and over oxide lining material; and planarizing the conductivematerial to a degree sufficient to isolate desired conductive materialrelative to other conductive material, the planarizing defining theconductive network.
 35. The method of forming a conductive network ofclaim 32, wherein the forming a conductive material comprises: etchinginto at least some oxide isolation region material; chemical vapordepositing an oxide lining material within the etched isolation regions;forming conductive material within the etched oxide isolation regionsand over oxide lining material; planarizing the conductive material to adegree sufficient to isolate desired conductive material relative toother conductive material, the planarizing defining the conductivenetwork; and removing selected conductive material to define a pluralityof interconnect lines.
 36. A method of forming conductive lines inelectrical contact with active area diffusion regions comprising:forming insulative material over a semiconductive substrate; forming aplurality of silicon-containing structures over the insulative material,individual silicon-containing structures having respective sidewalls,adjacent silicon-containing structure sidewalls defining respectivespaces therebetween; forming nitride-containing caps atop the individualsilicon-containing structures, forming insulative material in the spacesbetween individual adjacent silicon-containing structures; planarizingthe insulative material to be generally coplanar with thenitride-containing caps; etching at least some of the insulativematerial between individual adjacent silicon-containing structures to adegree sufficient to expose the respective sidewalls of the adjacentsilicon-containing structures, the etching defining respective troughsbetween the sidewalls having lateral widths in lateral width directions;depositing an oxide lining material within the troughs and overrespective sidewalls to a degree sufficient to fill about two thirds ofthe lateral width of the trough in the lateral width direction; formingconductive material over the substrate and in at least some of theremaining one third of the lateral width of the trough; planarizing theoxide lining material and the conductive material to be substantiallycoplanar with nitride-containing caps; recessing remaining conductivematerial within the trough to below an immediately adjacent planarsurface; masking selected substrate areas; removing conductive materialfrom unmasked substrate areas; forming insulative material over thesubstrate, the insulative material filling in the troughs from whichconductive material was removed and covering conductive material whichwas not removed; planarizing the insulative material to be substantiallycoplanar with the nitride-containing caps; removing thenitride-containing caps to outwardly expose respective outer surfaces ofthe silicon-containing structures, respective outer surfaces definingindividual active areas in which diffusion regions are to be formed;forming individual oxide layers over respective silicon-containingstructure outer surfaces; forming a polysilicon layer over the oxidelayers; planarizing the polysilicon layer; forming an oxide layer overthe polysilicon layer to provide stack structures over thesilicon-containing structures; patterning and etching the stackstructures to form individual gate structures over thesilicon-containing structures; forming sidewall spacers over respectivegate structure sidewalls; forming diffusion regions in thesilicon-containing structures adjacent individual gate structures;forming insulative material over the substrate; planarizing theinsulative material; patterning and etching the insulative material tooutwardly expose at least one diffusion region and at least some of theconductive material; and forming connective polysilicon material overthe one exposed diffusion region and the conductive material, theconnective material interconnecting the one exposed diffusion region andthe conductive material, the conductive material providing a conductiveline to the one diffusion region.
 37. Integrated memory circuitrycomprising: a substrate; a plurality of source/drain diffusion regionssupported by the substrate; a plurality of isolation oxide regionssupported by the substrate and interposed between and separating atleast some of the source/drain diffusion regions; and a plurality ofconductive lines supported by the substrate at least some of which beingoperatively connected with at least some of the source/drain diffusionregions and disposed within the isolation oxide regions.
 38. Theintegrated memory circuitry of claim 37 further comprising a pluralityof silicon-containing structures, the structures being separated byrespective isolation oxide regions and supporting respectivesource/drain diffusion regions.
 39. The integrated memory circuitry ofclaim 37, wherein the source/drain diffusion regions define respectiveouter surfaces and a predominant portion of at least some of theconductive lines which are disposed within the isolation oxide regionsare disposed elevationally below the source/drain diffusion regions'outer surfaces.